74AS00 DATASHEET PDF

74AS00 Quad 2-Input NAND Gate. Physical Dimensions inches (millimeters) unless otherwise noted (Continued). Lead Plastic Dual-In-Line Package ( PDIP). 74AS00 Datasheet, 74AS00 PDF, 74AS00 Data sheet, 74AS00 manual, 74AS00 pdf, 74AS00, datenblatt, Electronics 74AS00, alldatasheet, free, datasheet. description. These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functions Y = A • B or Y = A + B in positive logic.

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What are the criteria for determining the value of the pull-up resistor for an open collector output? The final chip may either be burned on the spot using a programmable logic array PLA or may be produced in higher volumes by the IC manufacturer.

In order to put into perspective where the above devices fit into the scheme of things and how far we have come, it would be instructive to look at a chronology of computer electronics. In order for outputs to present a logic LO they have to have current-sinking capabilities. Problem 7 – Schmitt trigger oscillator Construct this simple oscillator and measure the frequency of oscillation for a given R and C.

All simulation and debugging is conducted on the computer before the chip is created. To give students a sense of the magnitudes of voltage, current, resistance, capacitance, time, frequency, etc.

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The propagation delay inherent in gates can be useful for creating oscillatory circuits. This is useful for creating a party-line data bus or control bus whereby any one of several circuits may pull the line LO without causing damage to another active output. Observe here that the circuit elements associated with Q4 in the totem-pole circuit are 74ss00 and the collector of Q3 is left open-circuited, hence the name open-collector.

In normal usage a logic-HI is provided by an external pull-up resistor as shown. What is the range that would be considered a logic HI? Families can be characterized by the relationship between propagation-delay and power. What is the maximum current flowing through the outputs in c?

Problem 8 – Timer The dtasheet IC is a popular circuit for generating asymmetric rectangular waves.

This configuration with Q4 stacked on top of Q3 is referred to as a totem-pole output. What is the minimum and maximum values of R and C? Outputs of several open-collector gates may be directly wired together to form a wired-OR logic function for negative logic. In other words, when Q3 is closed, Q4 is open.

4D6 Lab Manual – Chapter 6

Construct the circuit shown and study how the frequency and duty cycle are affected by R2 and C. Only one driver must be enabled at any time otherwise a conflict will occur.

What is the minimum and maximum frequency of oscillation? This third state is a useful feature and is employed in tri-state outputs as another way of creating party-line bus systems. Digital logic is implemented using integrated circuits which are classified into families based on their 74a00 electronic structure. Regardless of the IC’s complexity or how it is created, basic knowledge of gates and flip-flops is still essential.

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What is the lowest value of R such that the output is ddatasheet HI? At any time, only one of the two switches is closed while the other is open.

(PDF) 74AS00 Datasheet download

Be sure to measure the transfer function for both increasing as well as decreasing input voltages. What is the voltage range that would be considered a logic LO?

Conversely, when Q3 is open, Q4 is closed. This is called the high impedance or Hi-Z state. Also shown in Figure 6. Draw the input and output waveforms timing diagram. If you examine a typical circuit board today you will find more use of large ICs with hundreds of pins and fewer style ICs.

Why is negative logic commonly used?